The present invention generally relates to high-speed data communications. More specifically, the invention relates to a system and method for combining a plurality of co-located physical layer transport links to form a virtual transport link that reuses standard asynchronous transfer mode (ATM) to physical layer interfaces (at both sides) while maintaining data sequence order.
With the advancement of technology, and the need for instantaneous information, the ability to transfer digital information from one computing device to another has become more and more important. Various line bonding techniques have been applied to provide bandwidth on demand, e.g., by applying multiple integrated services digital network (ISDN) connections in parallel and controlling the number of connections as a function of the expected load, to provide a better granularity between the T1 and T3 (or E1 and E3) standard telecommunication rates, and to provide more robust data transport systems by introducing redundancy.
Various line bonding techniques sometimes referred to as inverse multiplexing have been implemented. In bit level multiplexing, incoming data is stripped into individual bit streams. Each stripped bit stream is communicated individually across a physical transport link. At the receiving end of the link, framing is performed to realign the various stripped bit streams received on the various physical transport links into the original data stream. Bit level multiplexing is frequently performed through hardware implementations at the physical layer. As such, bit level multiplexing offers a great deal of flexibility in designing a multi-transport link. In addition, bit level multiplexing at the physical layer has the advantage of reducing data transfer latency when compared to multiplexing methods that operate at a protocol data unit (PDU) level. However, the flexibility of bit level multiplexing solutions requires the integration of hardware to identify, coordinate in time, and possibly error correct the various transmitted bit streams stripped from the original data stream. Bit level multiplexing solutions are difficult to implement when the various physical transport links operate at different bit rates. Still another drawback related to bit level multiplexing solutions is that they do not take advantage of the redundancy provided in the multiple physical transport links, if one link fails, every PDU is lost until an operable line bonding solution is configured. Because bit level multiplexing solutions are hardware solutions both the source and the destination devices must be configured with suitable hardware to strip and transmit a plurality of bit streams near a source computing device and receive and reassemble the transmitted bit streams near the destination computing device. The hardware intensive nature of bit level multiplexing solutions restricts such solutions to bandwidth on demand requests in proprietary intranets or between computing devices that use designated communication links that follow a particular bit sequencing standard to transfer information. As a result, bit level multiplexing solutions are not easily adaptable at the interface between an ATM layer device and a physical layer device.
Multi-link point to point protocol (PPP) is an Internet engineering task force (IETF) request for comments (RFC) communication standard that functions at a data packet level. Multi-link PPP inserts a sequence number to ensure that the virtual link preserves the original data packet sequence order at a destination-computing device. Multi-link PPP is a software solution that provides for the use of multiple simultaneous channels between systems, giving users bandwidth on demand. Multi-link PPP uses a combination of a four byte sequencing header with synchronization rules to split packets among parallel communication paths between systems such that the data packets do not become reordered at the destination device. Because multi-link PPP is a software solution both the source and the destination devices must be configured with a suitable processor and memory to store the necessary program code. This requirement limits multi-link PPP to the application of intersystem communication links as the additional hardware and firmware required to perform a multi-link PPP data transfer at an interface between an ATM layer device and a physical layer device makes such a transfer impractical as multi-link PPP is not directly suitable for ATM transport, even if ATM encapsulation in PPP could be envisaged.
Inverse multiplexing for ATM is an ATM forum standard defined for communication systems carrying ATM cells. The standard is quite complex and only applicable when the various transport links used in a transport bundle have nominally the same bit rate (e.g., all transport links are T1 links). Inverse multiplexing for ATM (IMA) is typically implemented by a mixture of hardware and software. IMA is complex both in defining the corresponding framing, typically performed in hardware, and in defining the control mechanism to establish and control bundles, usually performed in software.
In an IMA communication system, cell traffic is transported using a time division multiplexing technique over several channels (typically T1 or E1 data links). In a cell based IMA system, these ATM cells or payload cells are sent on each channel in a round-robin fashion using an identical period for each of the transport links. The IMA communication system relies on synchronized system clocks to inverse multiplex and reassembles data packets in the correct order.
For transmission of data beyond a local area, communication is typically achieved by transmitting data from source to destination computing devices through a network of intermediate switching nodes. These nodes are not concerned with the content of the data. Rather, their purpose is to provide a switching facility that will transport the data from node to node until the data reaches its target destination (e.g., a computing device). FIG. 1 illustrates a prior art communication system 1 that uses a plurality of ATM switching nodes to transfer data to and from a plurality of computing devices. More specifically, the communication system 1 comprises computing devices 15a-15d, herein labeled, xe2x80x9cA, B, C, Dxe2x80x9d in communication with each other via communication links 11 and an ATM switching network 10. As illustrated in FIG. 1, the ATM switching network 10 comprises a first ATM node 13a in communication with a second ATM node 13b via a plurality of links 16. As indicated above, these links 16 may comprise a plurality of standard T1, T3, E1, E3, or other data communication links with the same bit rate. The first ATM node 13a may comprise a first ATM switch 12a and a first ATM inverse multiplexer (AIM) 14a. The second ATM node 13b may comprise a second AIM 14b coupled to a second ATM switch 12b. As also illustrated in FIG. 1, the second ATM switch 12b of the second ATM node 13b may be in communication with computing devices 15c, 15d, xe2x80x9cCxe2x80x9d and xe2x80x9cDxe2x80x9d, via designated data communication links 11.
In a well known manner, a cell stream originating at computing device 15b (B) and having cell headers that designate computing device 15d (D) as their destination, may be transmitted along communication link 11 to the first ATM switch 12a within the first ATM node 13a of the ATM switching network 10. The first ATM switch 12a uses information in the cell header of each of the cells comprising the cell stream to identify an appropriate destination ATM switch 12b. Those skilled in the art will appreciate that an ATM switch 12a may be in communication with a plurality of remotely located ATM switches 12 via a plurality of designated AIM devices 14 and links 16. For simplicity of illustration and description, only two ATM switches 12a, 12b are illustrated in the ATM switching network 10 of FIG. 1. In the exemplary communication system illustrated in FIG. 1, the source ATM node 13a is communicatively coupled with the destination ATM node 13b via a plurality of links 16. Those skilled in the art will appreciate that ATM cells may traverse a plurality of interconnected ATM nodes 13 via links 16 on their way from a source computing device 15b to a destination computing device 15d. It will be further appreciated that individual ATM cells within the ATM cell stream may travel over significantly different physical paths within the ATM switching network 10.
Having identified the appropriate destination ATM node 13b in order to distribute the cells of the cell stream to computing device 15d (D), the first ATM switch 12a makes the various individual cells available to the first AIM 14a. The first AIM 14a applies each of the cells in a round-robin fashion to each of the available links 16 that connect the first ATM node 13a to the second ATM node 13b. The second AIM 14b within the second ATM node 13b receives each of the individual cells from each of the various links 16, reassembles the cell stream such that cell sequence integrity is preserved (i.e., the cell stream is reconstructed at the receiving end using the same round-robin sequence that was used to strip and transmit the various separate cells streams over the various links 16) and forwards the reassembled ATM cell stream to the second ATM switch 12b. Having been properly transferred and reassembled from a first or source ATM node 13a to a second or destination ATM node 13b within the ATM switching network 10, the individual cells within the cell stream are then transmitted from the second ATM switch 12b via the communication link 11 to the computing device 15d (D). It will be appreciated that the communication system 1 may be used to transmit video, voice, and text data between each of the interconnected computing devices 15. It will be further appreciated that the communication system 1 may comprise bi-directional communication links 11 and bi-directional ATM nodes 13 to permit simultaneous video, voice, and text data transfers to and from each of the computing devices coupled to the ATM switching network 10.
A digital subscriber line (DSL) communication system is but one example of a number of communication systems that may simultaneously transmit and receive digital data between two locations. Since a DSL communication system is capable of both transmitting and receiving digital data, a DSL communication system may serve as the communication link 11 between an ATM node 13 in an ATM switching network 10 and a computing device 15. In addition, a DSL communication system may serve as a portion of multi-channel communication link 16. In a DSL communication system, data is transmitted from a central office (CO) of the public switched telephone network (PSTN) to a customer premise (CP) via a transmission line, such as a two-wire twisted pair, and is transmitted from the CP to the CO as well, either simultaneously or in different communication sessions. The same transmission line might be utilized for data transfers by both sites or the transmission to and from the CO might occur on two separate lines.
Asymmetric DSL (ADSL) is an important variation of the basic DSL. ADSL gets its name from its inherent asymmetry between the various data rates. The upstream data rate (i.e., the data from the CP to the CO) is a factor of 10 smaller than the associated downstream data rate (i.e., the data from the CO to the CP). The asymmetry of ADSL suits transmission control protocol/Internet protocol (TCP/IP) data traffic quite well as it matches the expected upstream and downstream data rates associated with Internet technologies, such as server/client applications like web browsing and access in general. This is less true for LAN-LAN interconnection cases where IP is also used but where the data transmissions between the various computing devices are more uniform.
ADSL permits simultaneous plain old telephone system (POTS) operation along the same twisted-pair telephone line, thereby allowing DSL service providers easy access to potential customers already connected to the PSTN. In addition to the asymmetry of the upstream and downstream data paths, ADSL uses rate adaptation techniques to select an optimum rate based on individual twisted-pair telephone line conditions.
With ADSL transceivers, the maximum usable data rate may be determined by a number of factors. A first factor, the transceiver technology, may comprise the digital encoding and modulation scheme of the underlying ADSL communications standard, as well as, amplifier efficiency, and noise immunity associated with the hardware used to realize the DSL transceiver. A second factor may comprise the quality and distance of the twisted-pair telephone line comprising a local telephone service subscriber loop used to provide a data transmission medium between an ADSL transceiver in a CO and an associated CP-ADSL transceiver. A third factor may comprise the relative strength of local radio-frequency transmissions that may interfere with the ADSL frequency range. With rate adaptive DSL communications systems, such as ADSL, slower data rates can be traded in exchange for increased distances between COs and remotely located CPs.
In order to achieve higher data rates with a fixed distance or with a given non-rate adaptive DSL transceiver technology, two or more DSL lines may be combined. By way of example, high-speed DSL (HDSL) technology uses two pairs of twisted copper wire, HDSL transceivers, multiplexers and demultiplexers at each end of a communication link to provide T1 capacity service over two pairs of twisted copper conductors commonly used in local subscriber loops within the PSTN. The European version of HDSL binds three pairs of twisted copper conductors and their related transceivers, multiplexers, and demultiplexers to provide E1 capacity service.
In general, DSL implementations are configured such that each DSL transceiver at a CP has its own dedicated interface with associated customer premise equipment (CPE). In order to combine two or more DSLs at a CP an additional multiplexing unit is required. The additional multiplexing unit can be realized in a programmable microprocessor or with a dedicated application specific integrated circuit (ASIC). In either case, the number of components and the footprint of the system increase without a corresponding flexibility. HDSL bit multiplexing is strictly limited to predefined values and all links are synchronized using the same clock.
The prior art HDSL link illustrated in FIG. 2 is offered by way of example to highlight the additional interface equipment required as additional transmission media are added to increase the performance of a communications link. In this regard, FIG. 2 illustrates a basic HDSL network link architecture. As illustrated in FIG. 2, a HDSL network link 11 may comprise equipment located within a CO 20, equipment located within a CP 40, and HDSL interface equipment 30 as required within each location to transfer data to and from an ATM switch 13 (FIG. 1). More specifically, the central office 20 may comprise a plurality of trunk line interfaces 21, 23, and 25, herein labeled analog trunk card, digital trunk card, and optical trunk card respectively; a PSTN digital switch 22; and a plurality of HDSL termination unitsxe2x80x94central office (HTU-C) 24a, 24b, 24c, . . . , and 24x. As illustrated in FIG. 2, each HTU-C 24a, 24b, 24c, . . . , and 24x may be coupled via two twisted pair telephone transmission lines 31a, 31b to a dedicated HDSL termination unitxe2x80x94remote (HTU-R) 44c (one shown for simplicity of illustration). As also illustrated in FIG. 2, the combination of the HTU-C 24c, the two twisted pair telephone transmission lines 31a, 31b, and the HTU-R 44c may comprise the HDSL interface equipment 30. As further illustrated in FIG. 2, the CP 40 may comprise a customer interface 46 and customer premise equipment 48 which may contain one or more computing devices 15 (FIG. 1).
It is significant to note that downstream and upstream data transmissions that are transmitted across the HDSL network link 11 of FIG. 2 must be processed at the HTU-Rs 44 and the HTU-Cs 24 in order to ensure that data transmissions are inverse multiplexed and reconstructed into their original configuration. Each of the HTU-Rs 44 and the HTU-Cs 24 may further comprise a transceiver and a mapper (both not shown). At one end of the HDSL communications network 11, a first mapper may be used to inverse multiplex or distribute a data transmission across multiple transmit media (i.e., the twisted pair telephone transmission lines 31a, 31b). At the opposite or receiving end of the HDSL communications network 11, a second mapper may be used to multiplex or reconstruct the original data transmission. By way of example, a downstream data transmission may be inverse multiplexed such that a portion of the data is transmitted via the HTU-C 24c across a first twisted pair telephone transmission line 31a with the remaining portion of the data transmission sent via a second twisted pair telephone transmission line 31b. After the first and second portions of the data transmission are received and reconstructed by the HTU-R 44c, the first and second portions of the original data stream may be multiplexed before being forwarded to the customer interface 46 and the CPE 48. Often the customer interface 46 is implemented with a router having a port coupled with one or more HTU-Rs 44 and or other network interface devices.
It will be appreciated that the complexity and associated increase in the hardware and or software required to implement a prior art line bonding technique at the interface between ATM layer and physical transport layer devices may be significant factors that may prevent the success of a multi-channel communication link at this level. In light of the expected implementation and operational cost erosion for all data interface technologies, it is highly desirable to identify and implement communication links that exhibit increased performance with minimal added cost and complexity.
Accordingly, there is a need for an improved system and method that can increase the bandwidth of a communication link between two computing devices at the interface between ATM layer devices and various available physical layer transport links while minimizing installation and operational complexity, space requirements, and cost.
To provide an improved system that overcomes shortcomings noted above, the invention is a system and a method for combining multiple communication links at both sides of an ATM communications network. An improved ATM communications network in accordance with the present invention may achieve an overall higher data transfer rate by combining available communication transport links at the interface between an ATM layer device and a plurality of physical transport layer devices. The multi-channel communication link of the present invention achieves increased performance with a minimal hardware investment at the source and destination ATM network nodes. A multi-channel communication link in accordance with the present invention may comprise a source first-in first-out (FIFO) buffer, a source line multiplexer/demultiplexer, a plurality of communication links, a destination line multiplexer/demultiplexer, and a destination FIFO buffer.
The present invention can also be viewed as a method for transferring data between computing devices on a virtual transport link. In its broadest terms, the method can be described by the following steps: applying a sequence number to each packet to be transported in a time ordered fashion to create a corresponding transport protocol data unit; identifying the next available communication link; transmitting the next available transport protocol data unit on the identified communication link; receiving each transport protocol data unit; identifying the corresponding sequence number for each transport protocol data unit received; resequencing each received transport data unit as required; and releasing each packet to the destination device once all previous packets have been received and resequenced in the correct sequence order. In a variation of the method, a timeout process may be included for transport protocol data unit loss recovery. Using the timeout process, each packet may be sorted as in the broadest method then all cells up to the one generating the timeout may be released in sequence number order once the timeout period has been exceeded.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the claims.